# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: divergent_cycle_1
# CHECK-NEXT: CYCLES ASSSUMED DIVERGENT:
# CHECK-NEXT: depth=1: entries(bb.3 bb.1) bb.4 bb.2
# CHECK-NEXT: CYCLES WITH DIVERGENT EXIT:
# CHECK-NEXT: depth=2: entries(bb.4 bb.1) bb.2
# CHECK-NEXT: depth=1: entries(bb.3 bb.1) bb.4 bb.2



---
name:            divergent_cycle_1
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1, %bb.3
    %0:_(s32) = G_CONSTANT i32 0
    %1:_(s32) = G_CONSTANT i32 1

    %2:_(s32) = G_IMPLICIT_DEF
    %3:_(s32) = G_IMPLICIT_DEF

    %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
    %6:_(s1) = G_ICMP intpred(slt), %2(s32), %0(s32) ;uniform condition
    %7:_(s1) = G_ICMP intpred(eq), %4(s32), %0 ;divergent condition
    G_BRCOND %6(s1), %bb.1
    G_BR %bb.3

  bb.1:
    successors: %bb.2

  ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.0, %{{[0-9]*}}:_(s32), %bb.4
    %8:_(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.4
    %9:_(s32) = G_ADD %3(s32), %1(s32)
    G_BR %bb.2

  bb.2:
    successors: %bb.3, %bb.4

    %13:_(s32) = G_ADD %3(s32), %1(s32)
    G_BRCOND %7(s1), %bb.4
    G_BR %bb.3

  bb.3:
    successors: %bb.4

    %14:_(s32) = G_ADD %3(s32), %1(s32)
    G_BR %bb.4
  bb.4:
    successors: %bb.5, %bb.1

  ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.2, %{{[0-9]*}}:_(s32), %bb.3
    %15:_(s32) = G_PHI %13(s32), %bb.2, %14(s32), %bb.3
    %16:_(s32) = G_ADD %3(s32), %1(s32)
    G_BRCOND %6(s1), %bb.5
    G_BR %bb.1

  bb.5:
    %17:_(s32) = G_ADD %3(s32), %1(s32)
    S_ENDPGM 0
...

# CHECK-LABEL: MachineUniformityInfo for function: uniform_cycle_1
---
name:            uniform_cycle_1
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1, %bb.5
    %0:_(s32) = G_CONSTANT i32 0
    %1:_(s32) = G_CONSTANT i32 1

    %2:_(s32) = G_IMPLICIT_DEF
    %3:_(s32) = G_IMPLICIT_DEF

    %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
    %6:_(s1) = G_ICMP intpred(slt), %2(s32), %0(s32) ;uniform condition
    %7:_(s1) = G_ICMP intpred(eq), %4(s32), %0 ;divergent condition
    G_BRCOND %6(s1), %bb.1
    G_BR %bb.5

  bb.1:
    successors: %bb.2

  ; CHECK-NOT: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.0, %{{[0-9]*}}:_(s32), %bb.4
    %8:_(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.5
    %9:_(s32) = G_ADD %3(s32), %1(s32)
    G_BR %bb.2

  bb.2:
    successors: %bb.3, %bb.4

    %13:_(s32) = G_ADD %3(s32), %1(s32)
    G_BRCOND %7(s1), %bb.4
    G_BR %bb.3

  bb.3:
    successors: %bb.4

    %14:_(s32) = G_ADD %3(s32), %1(s32)
    G_BR %bb.4
  bb.4:
    successors: %bb.6, %bb.5

  ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.2, %{{[0-9]*}}:_(s32), %bb.3
    %15:_(s32) = G_PHI %13(s32), %bb.2, %14(s32), %bb.3
    %16:_(s32) = G_ADD %3(s32), %1(s32)
    G_BRCOND %6(s1), %bb.6
    G_BR %bb.5

  bb.5:
    successors: %bb.1
    %18:_(s32) = G_ADD %3(s32), %1(s32)
    G_BR %bb.1
  bb.6:
    %17:_(s32) = G_ADD %3(s32), %1(s32)
    S_ENDPGM 0
...
